F´ Flight Software - C/C++ Documentation
A framework for building embedded system applications to NASA flight quality standards.
AggregationMachineStateMachineAc.cpp
Go to the documentation of this file.
1 // ======================================================================
2 // \title AggregationMachineStateMachineAc.cpp
3 // \author Generated by fpp-to-cpp
4 // \brief cpp file for AggregationMachine state machine
5 // ======================================================================
6 
7 #include "Fw/Types/Assert.hpp"
9 
10 namespace Svc {
11 
12  // ----------------------------------------------------------------------
13  // Constructors and Destructors
14  // ----------------------------------------------------------------------
15 
18  {
19 
20  }
21 
24  {
25 
26  }
27 
28  // ----------------------------------------------------------------------
29  // Initialization
30  // ----------------------------------------------------------------------
31 
34  {
35  this->m_id = id;
36  // Enter the initial target of the state machine
37  this->enter_WAIT_STATUS(Signal::__FPRIME_AC_INITIAL_TRANSITION);
38  }
39 
40  // ----------------------------------------------------------------------
41  // Getter functions
42  // ----------------------------------------------------------------------
43 
45  getState() const
46  {
47  return this->m_state;
48  }
49 
50  // ----------------------------------------------------------------------
51  // Send signal functions
52  // ----------------------------------------------------------------------
53 
56  {
57  switch (this->m_state) {
58  case State::FILL:
59  if (this->guard_isNotEmpty(Signal::timeout)) {
60  // Do the actions for the transition
62  // Enter the target
63  this->enter_WAIT_STATUS(Signal::timeout);
64  }
65  break;
66  case State::WAIT_STATUS:
67  break;
68  default:
69  FW_ASSERT(0, static_cast<FwAssertArgType>(this->m_state));
70  break;
71  }
72  }
73 
76  {
77  switch (this->m_state) {
78  case State::FILL:
79  // Enter the target
80  this->enter_IS_FULL_THEN_SEND(Signal::fill, value);
81  break;
82  case State::WAIT_STATUS:
83  // Do the actions for the transition
84  this->action_doHold(Signal::fill, value);
85  break;
86  default:
87  FW_ASSERT(0, static_cast<FwAssertArgType>(this->m_state));
88  break;
89  }
90  }
91 
94  {
95  switch (this->m_state) {
96  case State::FILL:
97  // Do the actions for the transition
99  break;
100  case State::WAIT_STATUS:
101  // Enter the target
102  this->enter_IS_GOOD_STATUS(Signal::status, value);
103  break;
104  default:
105  FW_ASSERT(0, static_cast<FwAssertArgType>(this->m_state));
106  break;
107  }
108  }
109 
110  // ----------------------------------------------------------------------
111  // State and choice entry
112  // ----------------------------------------------------------------------
113 
114  void AggregationMachineStateMachineBase ::
115  enter_FILL(Signal signal)
116  {
117  // Update the state
118  this->m_state = State::FILL;
119  }
120 
121  void AggregationMachineStateMachineBase ::
122  enter_WAIT_STATUS(Signal signal)
123  {
124  // Update the state
125  this->m_state = State::WAIT_STATUS;
126  }
127 
128  void AggregationMachineStateMachineBase ::
129  enter_IS_GOOD_STATUS(
130  Signal signal,
131  const Fw::Success& value
132  )
133  {
134  if (this->guard_isGood(signal, value)) {
135  // Do the actions for the transition
136  this->action_doClear(signal);
137  // Enter the target
138  this->enter_FILL(signal);
139  }
140  else {
141  // Enter the target
142  this->enter_WAIT_STATUS(signal);
143  }
144  }
145 
146  void AggregationMachineStateMachineBase ::
147  enter_IS_FULL_THEN_SEND(
148  Signal signal,
149  const Svc::ComDataContextPair& value
150  )
151  {
152  if (this->guard_isFull(signal, value)) {
153  // Do the actions for the transition
154  this->action_doHold(signal, value);
155  this->action_doSend(signal);
156  // Enter the target
157  this->enter_WAIT_STATUS(signal);
158  }
159  else {
160  // Do the actions for the transition
161  this->action_doFill(signal, value);
162  // Enter the target
163  this->enter_FILL(signal);
164  }
165  }
166 
167 }
virtual void action_doHold(Signal signal, const Svc::ComDataContextPair &value)=0
Hold a buffer.
virtual void action_doClear(Signal signal)=0
Clear the buffer fill state, last status.
void sendSignal_status(const Fw::Success &value)
Status return.
void sendSignal_timeout()
Rate-group driven timeout signal.
I32 FwEnumStoreType
AggregationMachineStateMachineBase::State getState() const
Get the state.
void initBase(const FwEnumStoreType id)
Initialize the state machine.
virtual bool guard_isNotEmpty(Signal signal) const =0
Check if not empty.
virtual void action_doFill(Signal signal, const Svc::ComDataContextPair &value)=0
Fill the buffer with data.
virtual bool guard_isFull(Signal signal, const Svc::ComDataContextPair &value) const =0
Check if full.
void sendSignal_fill(const Svc::ComDataContextPair &value)
Fill buffer signal.
virtual void action_assertNoStatus(Signal signal)=0
Assert no status when in fill state.
virtual bool guard_isGood(Signal signal, const Fw::Success &value) const =0
Check if last status is good.
RateGroupDivider component implementation.
virtual void action_doSend(Signal signal)=0
Send the buffer data.
FpySequencer_SequencerStateMachineStateMachineBase::Signal Signal
#define FW_ASSERT(...)
Definition: Assert.hpp:14
Success/Failure.