7 #ifndef Svc_ActiveRateGroupComponentAc_HPP 8 #define Svc_ActiveRateGroupComponentAc_HPP 14 #if FW_ENABLE_TEXT_LOGGING == 1 125 #if FW_ENABLE_TEXT_LOGGING == 1 128 void set_LogText_OutputPort(
165 #if FW_PORT_SERIALIZATION 176 Fw::InputSerializePort* port
179 #if FW_ENABLE_TEXT_LOGGING == 1 182 void set_LogText_OutputPort(
184 Fw::InputSerializePort* port
192 Fw::InputSerializePort* port
198 Fw::InputSerializePort* port
203 #if FW_PORT_SERIALIZATION 214 Fw::InputSerializePort* port
220 Fw::InputSerializePort* port
233 const char* compName =
"" 266 #if FW_ENABLE_TEXT_LOGGING == 1 314 #if FW_ENABLE_TEXT_LOGGING == 1 319 bool isConnected_LogText_OutputPort(
504 static void m_p_CycleIn_in(
511 static void m_p_PingIn_in(
538 #if FW_ENABLE_TEXT_LOGGING == 1 570 bool m_first_update_RgMaxTime;
573 bool m_first_update_RgCycleSlips;
582 U32 m_last_RgMaxTime;
585 U32 m_last_RgCycleSlips;
void set_PingOut_OutputPort(FwIndexType portNum, Svc::InputPingPort *port)
Connect port to PingOut[portNum].
void tlmWrite_RgCycleSlips(U32 arg, Fw::Time _tlmTime=Fw::Time())
friend class ActiveRateGroupComponentBaseFriend
Friend class for white-box testing.
FwIndexType getNum_Time_OutputPorts() const
void CycleIn_handlerBase(FwIndexType portNum, Os::RawTime &cycleStart)
Handler base-class function for input port CycleIn.
void PingOut_out(FwIndexType portNum, U32 key)
Invoke output port PingOut.
FwIndexType getNum_PingOut_OutputPorts() const
PlatformSizeType FwSizeType
FwIndexType getNum_PingIn_InputPorts() const
virtual void PingIn_preMsgHook(FwIndexType portNum, U32 key)
Pre-message hook for async input port PingIn.
virtual ~ActiveRateGroupComponentBase()
Destroy ActiveRateGroupComponentBase object.
Warning event that rate group has had a cycle slip.
bool isConnected_Time_OutputPort(FwIndexType portNum)
PlatformIndexType FwIndexType
virtual void CycleIn_preMsgHook(FwIndexType portNum, Os::RawTime &cycleStart)
Pre-message hook for async input port CycleIn.
void set_Log_OutputPort(FwIndexType portNum, Fw::InputLogPort *port)
Connect port to Log[portNum].
void init()
Object initializer.
ActiveRateGroupComponentBase(const char *compName="")
Construct ActiveRateGroupComponentBase object.
void set_RateGroupMemberOut_OutputPort(FwIndexType portNum, Svc::InputSchedPort *port)
Connect port to RateGroupMemberOut[portNum].
bool isConnected_Log_OutputPort(FwIndexType portNum)
Channel ID for RgMaxTime.
void log_DIAGNOSTIC_RateGroupStarted() const
FwIndexType getNum_RateGroupMemberOut_OutputPorts() const
FwIndexType getNum_Tlm_OutputPorts() const
bool isConnected_Tlm_OutputPort(FwIndexType portNum)
void tlmWrite_RgMaxTime(U32 arg, Fw::Time _tlmTime=Fw::Time())
Channel ID for RgCycleSlips.
C++-compatible configuration header for fprime configuration.
void log_WARNING_HI_RateGroupCycleSlip(U32 cycle) const
void set_Time_OutputPort(FwIndexType portNum, Fw::InputTimePort *port)
Connect port to Time[portNum].
bool isConnected_RateGroupMemberOut_OutputPort(FwIndexType portNum)
virtual void CycleIn_handler(FwIndexType portNum, Os::RawTime &cycleStart)=0
Handler for input port CycleIn.
Auto-generated base for ActiveRateGroup component.
FwIndexType getNum_CycleIn_InputPorts() const
Svc::InputPingPort * get_PingIn_InputPort(FwIndexType portNum)
virtual void PingIn_handler(FwIndexType portNum, U32 key)=0
Handler for input port PingIn.
Informational event that rate group has started.
FwIndexType getNum_Log_OutputPorts() const
bool isConnected_PingOut_OutputPort(FwIndexType portNum)
Svc::InputCyclePort * get_CycleIn_InputPort(FwIndexType portNum)
void RateGroupMemberOut_out(FwIndexType portNum, U32 context)
Invoke output port RateGroupMemberOut.
void set_Tlm_OutputPort(FwIndexType portNum, Fw::InputTlmPort *port)
Connect port to Tlm[portNum].
void PingIn_handlerBase(FwIndexType portNum, U32 key)
Handler base-class function for input port PingIn.