7 #ifndef Svc_ActivePhaserComponentAc_HPP 8 #define Svc_ActivePhaserComponentAc_HPP 16 #if FW_ENABLE_TEXT_LOGGING == 1 118 #if FW_ENABLE_TEXT_LOGGING == 1 121 void set_logTextOut_OutputPort(
152 #if FW_PORT_SERIALIZATION 163 Fw::InputSerializePort* port
166 #if FW_ENABLE_TEXT_LOGGING == 1 169 void set_logTextOut_OutputPort(
171 Fw::InputSerializePort* port
179 Fw::InputSerializePort* port
185 Fw::InputSerializePort* port
190 #if FW_PORT_SERIALIZATION 201 Fw::InputSerializePort* port
214 const char* compName =
"" 242 #if FW_ENABLE_TEXT_LOGGING == 1 285 #if FW_ENABLE_TEXT_LOGGING == 1 290 bool isConnected_logTextOut_OutputPort(
447 static void m_p_CycleIn_in(
471 #if FW_ENABLE_TEXT_LOGGING == 1 500 std::atomic<FwIndexType> m_MissedDeadlineThrottle;
void set_tlmOut_OutputPort(FwIndexType portNum, Fw::InputTlmPort *port)
Connect port to tlmOut[portNum].
PlatformSizeType FwSizeType
void set_logOut_OutputPort(FwIndexType portNum, Fw::InputLogPort *port)
Connect port to logOut[portNum].
void set_PhaserMemberOut_OutputPort(FwIndexType portNum, Svc::InputSchedPort *port)
Connect port to PhaserMemberOut[portNum].
bool isConnected_PhaserMemberOut_OutputPort(FwIndexType portNum)
void init()
Object initializer.
Warning event that rate group has had a missed deadline.
bool isConnected_logOut_OutputPort(FwIndexType portNum)
FwIndexType getNum_logOut_OutputPorts() const
ActivePhaserComponentBase(const char *compName="")
Construct ActivePhaserComponentBase object.
virtual ~ActivePhaserComponentBase()
Destroy ActivePhaserComponentBase object.
friend class ActivePhaserTester
Friend class tester implementation to support white-box testing.
FwIndexType getNum_tlmOut_OutputPorts() const
void PhaserMemberOut_out(FwIndexType portNum, U32 context)
Invoke output port PhaserMemberOut.
void Tick_internalInterfaceInvoke()
Internal interface base-class function for Tick.
Svc::InputCyclePort * get_CycleIn_InputPort(FwIndexType portNum)
FwIndexType getNum_PhaserMemberOut_OutputPorts() const
friend class ActivePhaserTesterBase
Friend class tester to support autocoded test harness.
bool isConnected_timeCaller_OutputPort(FwIndexType portNum)
Throttle reset count for MissedDeadline.
Auto-generated base for ActivePhaser component.
PlatformIndexType FwIndexType
virtual void Tick_internalInterfaceHandler()=0
Internal interface handler for Tick.
void log_WARNING_HI_MissedDeadline_ThrottleClear()
Reset throttle value for MissedDeadline.
void CycleIn_handlerBase(FwIndexType portNum, Os::RawTime &cycleStart)
Handler base-class function for input port CycleIn.
virtual void CycleIn_handler(FwIndexType portNum, Os::RawTime &cycleStart)=0
Handler for input port CycleIn.
RateGroupDivider component implementation.
void set_timeCaller_OutputPort(FwIndexType portNum, Fw::InputTimePort *port)
Connect port to timeCaller[portNum].
virtual void CycleIn_preMsgHook(FwIndexType portNum, Os::RawTime &cycleStart)
Pre-message hook for async input port CycleIn.
void start(FwTaskPriorityType priority=Os::Task::TASK_PRIORITY_DEFAULT, FwSizeType stackSize=Os::Task::TASK_DEFAULT, FwSizeType cpuAffinity=Os::Task::TASK_DEFAULT, FwTaskIdType identifier=static_cast< FwTaskIdType >(Os::Task::TASK_DEFAULT))
called by instantiator when task is to be started
FwIndexType getNum_timeCaller_OutputPorts() const
bool isConnected_tlmOut_OutputPort(FwIndexType portNum)
void log_WARNING_HI_MissedDeadline(FwIndexType p, U32 start, U32 length, U32 ticks)
FwIndexType getNum_CycleIn_InputPorts() const