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RateGroupDriverComponentAc.cpp
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1 // ======================================================================
2 // \title RateGroupDriverComponentAc.cpp
3 // \author Generated by fpp-to-cpp
4 // \brief cpp file for RateGroupDriver component base class
5 // ======================================================================
6 
7 #include "Fw/Types/Assert.hpp"
9 #if FW_ENABLE_TEXT_LOGGING
10 #include "Fw/Types/String.hpp"
11 #endif
13 
14 namespace Svc {
15 
16  // ----------------------------------------------------------------------
17  // Component initialization
18  // ----------------------------------------------------------------------
19 
22  {
23  // Initialize base class
25 
26  // Connect input port CycleIn
27  for (
28  FwIndexType port = 0;
29  port < static_cast<FwIndexType>(this->getNum_CycleIn_InputPorts());
30  port++
31  ) {
32  this->m_CycleIn_InputPort[port].init();
33  this->m_CycleIn_InputPort[port].addCallComp(
34  this,
35  m_p_CycleIn_in
36  );
37  this->m_CycleIn_InputPort[port].setPortNum(port);
38 
39 #if FW_OBJECT_NAMES == 1
40  Fw::ObjectName portName;
41  portName.format(
42  "%s_CycleIn_InputPort[%" PRI_FwIndexType "]",
43  this->m_objName.toChar(),
44  port
45  );
46  this->m_CycleIn_InputPort[port].setObjName(portName.toChar());
47 #endif
48  }
49 
50  // Connect output port CycleOut
51  for (
52  FwIndexType port = 0;
53  port < static_cast<FwIndexType>(this->getNum_CycleOut_OutputPorts());
54  port++
55  ) {
56  this->m_CycleOut_OutputPort[port].init();
57 
58 #if FW_OBJECT_NAMES == 1
59  Fw::ObjectName portName;
60  portName.format(
61  "%s_CycleOut_OutputPort[%" PRI_FwIndexType "]",
62  this->m_objName.toChar(),
63  port
64  );
65  this->m_CycleOut_OutputPort[port].setObjName(portName.toChar());
66 #endif
67  }
68  }
69 
70  // ----------------------------------------------------------------------
71  // Getters for typed input ports
72  // ----------------------------------------------------------------------
73 
76  {
77  FW_ASSERT(
78  (0 <= portNum) && (portNum < this->getNum_CycleIn_InputPorts()),
79  static_cast<FwAssertArgType>(portNum)
80  );
81 
82  return &this->m_CycleIn_InputPort[portNum];
83  }
84 
85  // ----------------------------------------------------------------------
86  // Connect typed input ports to typed output ports
87  // ----------------------------------------------------------------------
88 
91  FwIndexType portNum,
93  )
94  {
95  FW_ASSERT(
96  (0 <= portNum) && (portNum < this->getNum_CycleOut_OutputPorts()),
97  static_cast<FwAssertArgType>(portNum)
98  );
99 
100  this->m_CycleOut_OutputPort[portNum].addCallPort(port);
101  }
102 
103 #if FW_PORT_SERIALIZATION
104 
105  // ----------------------------------------------------------------------
106  // Connect serial input ports to typed output ports
107  // ----------------------------------------------------------------------
108 
111  FwIndexType portNum,
112  Fw::InputSerializePort* port
113  )
114  {
115  FW_ASSERT(
116  (0 <= portNum) && (portNum < this->getNum_CycleOut_OutputPorts()),
117  static_cast<FwAssertArgType>(portNum)
118  );
119 
120  this->m_CycleOut_OutputPort[portNum].registerSerialPort(port);
121  }
122 
123 #endif
124 
125  // ----------------------------------------------------------------------
126  // Component construction and destruction
127  // ----------------------------------------------------------------------
128 
130  RateGroupDriverComponentBase(const char* compName) :
131  Fw::PassiveComponentBase(compName)
132  {
133 
134  }
135 
138  {
139 
140  }
141 
142  // ----------------------------------------------------------------------
143  // Connection status queries for typed output ports
144  // ----------------------------------------------------------------------
145 
148  {
149  FW_ASSERT(
150  (0 <= portNum) && (portNum < this->getNum_CycleOut_OutputPorts()),
151  static_cast<FwAssertArgType>(portNum)
152  );
153 
154  return this->m_CycleOut_OutputPort[portNum].isConnected();
155  }
156 
157  // ----------------------------------------------------------------------
158  // Port handler base-class functions for typed input ports
159  //
160  // Call these functions directly to bypass the corresponding ports
161  // ----------------------------------------------------------------------
162 
165  FwIndexType portNum,
166  Os::RawTime& cycleStart
167  )
168  {
169  // Make sure port number is valid
170  FW_ASSERT(
171  (0 <= portNum) && (portNum < this->getNum_CycleIn_InputPorts()),
172  static_cast<FwAssertArgType>(portNum)
173  );
174 
175  // Call handler function
176  this->CycleIn_handler(
177  portNum,
178  cycleStart
179  );
180  }
181 
182  // ----------------------------------------------------------------------
183  // Invocation functions for typed output ports
184  // ----------------------------------------------------------------------
185 
188  FwIndexType portNum,
189  Os::RawTime& cycleStart
190  )
191  {
192  FW_ASSERT(
193  (0 <= portNum) && (portNum < this->getNum_CycleOut_OutputPorts()),
194  static_cast<FwAssertArgType>(portNum)
195  );
196 
197  FW_ASSERT(
198  this->m_CycleOut_OutputPort[portNum].isConnected(),
199  static_cast<FwAssertArgType>(portNum)
200  );
201  this->m_CycleOut_OutputPort[portNum].invoke(
202  cycleStart
203  );
204  }
205 
206  // ----------------------------------------------------------------------
207  // Calls for messages received on typed input ports
208  // ----------------------------------------------------------------------
209 
210  void RateGroupDriverComponentBase ::
211  m_p_CycleIn_in(
212  Fw::PassiveComponentBase* callComp,
213  FwIndexType portNum,
214  Os::RawTime& cycleStart
215  )
216  {
217  FW_ASSERT(callComp);
218  RateGroupDriverComponentBase* compPtr = static_cast<RateGroupDriverComponentBase*>(callComp);
219  compPtr->CycleIn_handlerBase(
220  portNum,
221  cycleStart
222  );
223  }
224 
225 }
void addCallComp(Fw::PassiveComponentBase *callComp, CompFuncPtr funcPtr)
Register a component.
Definition: CyclePortAc.cpp:62
I32 FwEnumStoreType
virtual ~RateGroupDriverComponentBase()
Destroy RateGroupDriverComponentBase object.
void set_CycleOut_OutputPort(FwIndexType portNum, Svc::InputCyclePort *port)
Connect port to CycleOut[portNum].
void init()
Object initializer.
Definition: ObjBase.cpp:24
virtual void CycleIn_handler(FwIndexType portNum, Os::RawTime &cycleStart)=0
Handler for input port CycleIn.
void addCallPort(InputCyclePort *callPort)
Register an input port.
Auto-generated base for RateGroupDriver component.
void CycleOut_out(FwIndexType portNum, Os::RawTime &cycleStart)
Invoke output port CycleOut.
void CycleIn_handlerBase(FwIndexType portNum, Os::RawTime &cycleStart)
Handler base-class function for input port CycleIn.
const char * toChar() const
Convert to a C-style char*.
Definition: ObjectName.hpp:50
bool isConnected() const
Definition: PortBase.cpp:38
bool isConnected_CycleOut_OutputPort(FwIndexType portNum)
Svc::InputCyclePort * get_CycleIn_InputPort(FwIndexType portNum)
#define PRI_FwIndexType
FormatStatus format(const CHAR *formatString,...)
write formatted string to buffer
Definition: StringBase.cpp:39
RateGroupDriverComponentBase(const char *compName="")
Construct RateGroupDriverComponentBase object.
void setPortNum(FwIndexType portNum)
void init()
Initialization function.
void init()
Initialization function.
Definition: CyclePortAc.cpp:56
static constexpr FwIndexType getNum_CycleIn_InputPorts()
PlatformIndexType FwIndexType
RateGroupDivider component implementation.
void invoke(Os::RawTime &cycleStart) const
Invoke a port interface.
Implementation of malloc based allocator.
static constexpr FwIndexType getNum_CycleOut_OutputPorts()
#define FW_ASSERT(...)
Definition: Assert.hpp:14