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RateGroupDriverComponentAc.cpp
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1 // ======================================================================
2 // \title RateGroupDriverComponentAc.cpp
3 // \author Generated by fpp-to-cpp
4 // \brief cpp file for RateGroupDriver component base class
5 // ======================================================================
6 
7 #include "Fw/Types/Assert.hpp"
9 #if FW_ENABLE_TEXT_LOGGING
10 #include "Fw/Types/String.hpp"
11 #endif
13 
14 namespace Svc {
15 
16  // ----------------------------------------------------------------------
17  // Component initialization
18  // ----------------------------------------------------------------------
19 
22  {
23  // Initialize base class
25 
26 #if !FW_DIRECT_PORT_CALLS
27  // Connect input port CycleIn
28  for (
29  FwIndexType port = 0;
30  port < static_cast<FwIndexType>(this->getNum_CycleIn_InputPorts());
31  port++
32  ) {
33  this->m_CycleIn_InputPort[port].init();
34  this->m_CycleIn_InputPort[port].addCallComp(
35  this,
36  m_p_CycleIn_in
37  );
38  this->m_CycleIn_InputPort[port].setPortNum(port);
39 
40 #if FW_OBJECT_NAMES == 1
41  Fw::ObjectName portName;
42  portName.format(
43  "%s_CycleIn_InputPort[%" PRI_FwIndexType "]",
44  this->m_objName.toChar(),
45  port
46  );
47  this->m_CycleIn_InputPort[port].setObjName(portName.toChar());
48 #endif
49  }
50 #endif
51 
52 #if !FW_DIRECT_PORT_CALLS
53  // Connect output port CycleOut
54  for (
55  FwIndexType port = 0;
56  port < static_cast<FwIndexType>(this->getNum_CycleOut_OutputPorts());
57  port++
58  ) {
59  this->m_CycleOut_OutputPort[port].init();
60 
61 #if FW_OBJECT_NAMES == 1
62  Fw::ObjectName portName;
63  portName.format(
64  "%s_CycleOut_OutputPort[%" PRI_FwIndexType "]",
65  this->m_objName.toChar(),
66  port
67  );
68  this->m_CycleOut_OutputPort[port].setObjName(portName.toChar());
69 #endif
70  }
71 #endif
72  }
73 
74 #if !FW_DIRECT_PORT_CALLS
75 
76  // ----------------------------------------------------------------------
77  // Getters for typed input ports
78  // ----------------------------------------------------------------------
79 
82  {
83  FW_ASSERT(
84  (0 <= portNum) && (portNum < this->getNum_CycleIn_InputPorts()),
85  static_cast<FwAssertArgType>(portNum)
86  );
87 
88  return &this->m_CycleIn_InputPort[portNum];
89  }
90 
91 #endif
92 
93 #if !FW_DIRECT_PORT_CALLS
94 
95  // ----------------------------------------------------------------------
96  // Connect typed input ports to typed output ports
97  // ----------------------------------------------------------------------
98 
101  FwIndexType portNum,
102  Svc::InputCyclePort* port
103  )
104  {
105  FW_ASSERT(
106  (0 <= portNum) && (portNum < this->getNum_CycleOut_OutputPorts()),
107  static_cast<FwAssertArgType>(portNum)
108  );
109 
110  this->m_CycleOut_OutputPort[portNum].addCallPort(port);
111  }
112 
113 #endif
114 
115 #if !FW_DIRECT_PORT_CALLS && FW_PORT_SERIALIZATION
116 
117  // ----------------------------------------------------------------------
118  // Connect serial input ports to typed output ports
119  // ----------------------------------------------------------------------
120 
123  FwIndexType portNum,
124  Fw::InputSerializePort* port
125  )
126  {
127  FW_ASSERT(
128  (0 <= portNum) && (portNum < this->getNum_CycleOut_OutputPorts()),
129  static_cast<FwAssertArgType>(portNum)
130  );
131 
132  this->m_CycleOut_OutputPort[portNum].registerSerialPort(port);
133  }
134 
135 #endif
136 
137  // ----------------------------------------------------------------------
138  // Component construction and destruction
139  // ----------------------------------------------------------------------
140 
142  RateGroupDriverComponentBase(const char* compName) :
143  Fw::PassiveComponentBase(compName)
144  {
145 
146  }
147 
150  {
151 
152  }
153 
154 #if !FW_DIRECT_PORT_CALLS
155 
156  // ----------------------------------------------------------------------
157  // Connection status queries for typed output ports
158  // ----------------------------------------------------------------------
159 
162  {
163  FW_ASSERT(
164  (0 <= portNum) && (portNum < this->getNum_CycleOut_OutputPorts()),
165  static_cast<FwAssertArgType>(portNum)
166  );
167 
168  return this->m_CycleOut_OutputPort[portNum].isConnected();
169  }
170 
171 #endif
172 
173  // ----------------------------------------------------------------------
174  // Port handler base-class functions for typed input ports
175  //
176  // Call these functions directly to bypass the corresponding ports
177  // ----------------------------------------------------------------------
178 
181  FwIndexType portNum,
182  Os::RawTime& cycleStart
183  )
184  {
185  // Make sure port number is valid
186  FW_ASSERT(
187  (0 <= portNum) && (portNum < this->getNum_CycleIn_InputPorts()),
188  static_cast<FwAssertArgType>(portNum)
189  );
190 
191  // Call handler function
192  this->CycleIn_handler(
193  portNum,
194  cycleStart
195  );
196  }
197 
198 #if !FW_DIRECT_PORT_CALLS
199 
200  // ----------------------------------------------------------------------
201  // Invocation functions for typed output ports
202  // ----------------------------------------------------------------------
203 
206  FwIndexType portNum,
207  Os::RawTime& cycleStart
208  ) const
209  {
210  FW_ASSERT(
211  (0 <= portNum) && (portNum < this->getNum_CycleOut_OutputPorts()),
212  static_cast<FwAssertArgType>(portNum)
213  );
214 
215  FW_ASSERT(
216  this->m_CycleOut_OutputPort[portNum].isConnected(),
217  static_cast<FwAssertArgType>(portNum)
218  );
219  this->m_CycleOut_OutputPort[portNum].invoke(
220  cycleStart
221  );
222  }
223 
224 #endif
225 
226  // ----------------------------------------------------------------------
227  // Calls for messages received on typed input ports
228  // ----------------------------------------------------------------------
229 
230  void RateGroupDriverComponentBase ::
231  m_p_CycleIn_in(
232  Fw::PassiveComponentBase* callComp,
233  FwIndexType portNum,
234  Os::RawTime& cycleStart
235  )
236  {
237  FW_ASSERT(callComp);
238  RateGroupDriverComponentBase* compPtr = static_cast<RateGroupDriverComponentBase*>(callComp);
239  compPtr->CycleIn_handlerBase(
240  portNum,
241  cycleStart
242  );
243  }
244 
245 }
bool isConnected_CycleOut_OutputPort(FwIndexType portNum) const
void addCallComp(Fw::PassiveComponentBase *callComp, CompFuncPtr funcPtr)
Register a component.
Definition: CyclePortAc.cpp:79
I32 FwEnumStoreType
virtual ~RateGroupDriverComponentBase()
Destroy RateGroupDriverComponentBase object.
void set_CycleOut_OutputPort(FwIndexType portNum, Svc::InputCyclePort *port)
Connect port to CycleOut[portNum].
void init()
Object initializer.
Definition: ObjBase.cpp:24
virtual void CycleIn_handler(FwIndexType portNum, Os::RawTime &cycleStart)=0
Handler for input port CycleIn.
void addCallPort(InputCyclePort *callPort)
Register an input port.
Auto-generated base for RateGroupDriver component.
void CycleIn_handlerBase(FwIndexType portNum, Os::RawTime &cycleStart)
Handler base-class function for input port CycleIn.
const char * toChar() const
Convert to a C-style char*.
Definition: ObjectName.hpp:50
bool isConnected() const
Definition: PortBase.cpp:38
Svc::InputCyclePort * get_CycleIn_InputPort(FwIndexType portNum)
#define PRI_FwIndexType
FormatStatus format(const CHAR *formatString,...)
write formatted string to buffer
Definition: StringBase.cpp:39
RateGroupDriverComponentBase(const char *compName="")
Construct RateGroupDriverComponentBase object.
void setPortNum(FwIndexType portNum)
void init()
Initialization function.
void init()
Initialization function.
Definition: CyclePortAc.cpp:73
static constexpr FwIndexType getNum_CycleIn_InputPorts()
PlatformIndexType FwIndexType
RateGroupDivider component implementation.
void CycleOut_out(FwIndexType portNum, Os::RawTime &cycleStart) const
Invoke output port CycleOut.
void invoke(Os::RawTime &cycleStart) const
Invoke a port connection.
Implementation of malloc based allocator.
static constexpr FwIndexType getNum_CycleOut_OutputPorts()
#define FW_ASSERT(...)
Definition: Assert.hpp:14