RateGroupDriverComponentAc.hpp

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// ======================================================================
// \title  RateGroupDriverComponentAc.hpp
// \author Generated by fpp-to-cpp
// \brief  hpp file for RateGroupDriver component base class
// ======================================================================

#ifndef Svc_RateGroupDriverComponentAc_HPP
#define Svc_RateGroupDriverComponentAc_HPP

#include "Fw/Comp/ActiveComponentBase.hpp"
#include "Fw/FPrimeBasicTypes.hpp"
#if !FW_DIRECT_PORT_CALLS
#include "Fw/Port/InputSerializePort.hpp"
#endif
#if !FW_DIRECT_PORT_CALLS
#include "Fw/Port/OutputSerializePort.hpp"
#endif
#include "Svc/Cycle/CyclePortAc.hpp"

namespace Svc {

  class RateGroupDriverComponentBase :
    public Fw::PassiveComponentBase
  {

      // ----------------------------------------------------------------------
      // Friend classes
      // ----------------------------------------------------------------------

      friend class RateGroupDriverTesterBase;
      friend class RateGroupDriverTester;

    protected:

      // ----------------------------------------------------------------------
      // Constants
      // ----------------------------------------------------------------------

      enum {
        NUM_CYCLEIN_INPUT_PORTS = 1,
      };

      enum {
        NUM_CYCLEOUT_OUTPUT_PORTS = 3,
      };

    public:

      // ----------------------------------------------------------------------
      // Component initialization
      // ----------------------------------------------------------------------

      void init(
          FwEnumStoreType instance = 0 
      );

#if !FW_DIRECT_PORT_CALLS

    public:

      // ----------------------------------------------------------------------
      // Getters for typed input ports
      // ----------------------------------------------------------------------

      Svc::InputCyclePort* get_CycleIn_InputPort(
          FwIndexType portNum 
      );

#endif

#if !FW_DIRECT_PORT_CALLS

    public:

      // ----------------------------------------------------------------------
      // Connect typed input ports to typed output ports
      // ----------------------------------------------------------------------

      void set_CycleOut_OutputPort(
          FwIndexType portNum, 
          Svc::InputCyclePort* port 
      );

#endif

#if !FW_DIRECT_PORT_CALLS && FW_PORT_SERIALIZATION

    public:

      // ----------------------------------------------------------------------
      // Connect serial input ports to typed output ports
      // ----------------------------------------------------------------------

      void set_CycleOut_OutputPort(
          FwIndexType portNum, 
          Fw::InputSerializePort* port 
      );

#endif

    protected:

      // ----------------------------------------------------------------------
      // Component construction and destruction
      // ----------------------------------------------------------------------

      RateGroupDriverComponentBase(
          const char* compName = "" 
      );

      virtual ~RateGroupDriverComponentBase();

    protected:

      // ----------------------------------------------------------------------
      // Getters for numbers of typed input ports
      // ----------------------------------------------------------------------

      static constexpr FwIndexType getNum_CycleIn_InputPorts() {
        return NUM_CYCLEIN_INPUT_PORTS;
      }

    protected:

      // ----------------------------------------------------------------------
      // Getters for numbers of typed output ports
      // ----------------------------------------------------------------------

      static constexpr FwIndexType getNum_CycleOut_OutputPorts() {
        return NUM_CYCLEOUT_OUTPUT_PORTS;
      }

    protected:

      // ----------------------------------------------------------------------
      // Connection status queries for typed output ports
      // ----------------------------------------------------------------------

      bool isConnected_CycleOut_OutputPort(
          FwIndexType portNum 
      ) const;

    protected:

      // ----------------------------------------------------------------------
      // Handlers to implement for typed input ports
      // ----------------------------------------------------------------------

      virtual void CycleIn_handler(
          FwIndexType portNum, 
          Os::RawTime& cycleStart 
      ) = 0;

#if FW_DIRECT_PORT_CALLS
    public:
#else
    protected:
#endif

      // ----------------------------------------------------------------------
      // Port handler base-class functions for typed input ports
      //
      // Call these functions directly to bypass the corresponding ports
      // ----------------------------------------------------------------------

      void CycleIn_handlerBase(
          FwIndexType portNum, 
          Os::RawTime& cycleStart 
      );

    protected:

      // ----------------------------------------------------------------------
      // Invocation functions for typed output ports
      // ----------------------------------------------------------------------

      void CycleOut_out(
          FwIndexType portNum, 
          Os::RawTime& cycleStart 
      ) const;

    private:

      // ----------------------------------------------------------------------
      // Calls for messages received on typed input ports
      // ----------------------------------------------------------------------

      static void m_p_CycleIn_in(
          Fw::PassiveComponentBase* callComp, 
          FwIndexType portNum, 
          Os::RawTime& cycleStart 
      );

#if !FW_DIRECT_PORT_CALLS

    private:

      // ----------------------------------------------------------------------
      // Typed input ports
      // ----------------------------------------------------------------------

      Svc::InputCyclePort m_CycleIn_InputPort[NUM_CYCLEIN_INPUT_PORTS];

#endif

#if !FW_DIRECT_PORT_CALLS

    private:

      // ----------------------------------------------------------------------
      // Typed output ports
      // ----------------------------------------------------------------------

      Svc::OutputCyclePort m_CycleOut_OutputPort[NUM_CYCLEOUT_OUTPUT_PORTS];

#endif

  };

}

#endif