PassiveRateGroupComponentAc.cpp

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// ======================================================================
// \title  PassiveRateGroupComponentAc.cpp
// \author Generated by fpp-to-cpp
// \brief  cpp file for PassiveRateGroup component base class
// ======================================================================

#include "Fw/Types/Assert.hpp"
#include "Fw/Types/ExternalString.hpp"
#if FW_ENABLE_TEXT_LOGGING
#include "Fw/Types/String.hpp"
#endif
#include "Svc/PassiveRateGroup/PassiveRateGroupComponentAc.hpp"

namespace Svc {

  // ----------------------------------------------------------------------
  // Component initialization
  // ----------------------------------------------------------------------

  void PassiveRateGroupComponentBase ::
    init(FwEnumStoreType instance)
  {
    // Initialize base class
    Fw::PassiveComponentBase::init(instance);

    // Connect input port CycleIn
    for (
      FwIndexType port = 0;
      port < static_cast<FwIndexType>(this->getNum_CycleIn_InputPorts());
      port++
    ) {
      this->m_CycleIn_InputPort[port].init();
      this->m_CycleIn_InputPort[port].addCallComp(
        this,
        m_p_CycleIn_in
      );
      this->m_CycleIn_InputPort[port].setPortNum(port);

#if FW_OBJECT_NAMES == 1
      Fw::ObjectName portName;
      portName.format(
        "%s_CycleIn_InputPort[%" PRI_FwIndexType "]",
        this->m_objName.toChar(),
        port
      );
      this->m_CycleIn_InputPort[port].setObjName(portName.toChar());
#endif
    }

    // Connect output port Time
    for (
      FwIndexType port = 0;
      port < static_cast<FwIndexType>(this->getNum_Time_OutputPorts());
      port++
    ) {
      this->m_Time_OutputPort[port].init();

#if FW_OBJECT_NAMES == 1
      Fw::ObjectName portName;
      portName.format(
        "%s_Time_OutputPort[%" PRI_FwIndexType "]",
        this->m_objName.toChar(),
        port
      );
      this->m_Time_OutputPort[port].setObjName(portName.toChar());
#endif
    }

    // Connect output port Tlm
    for (
      FwIndexType port = 0;
      port < static_cast<FwIndexType>(this->getNum_Tlm_OutputPorts());
      port++
    ) {
      this->m_Tlm_OutputPort[port].init();

#if FW_OBJECT_NAMES == 1
      Fw::ObjectName portName;
      portName.format(
        "%s_Tlm_OutputPort[%" PRI_FwIndexType "]",
        this->m_objName.toChar(),
        port
      );
      this->m_Tlm_OutputPort[port].setObjName(portName.toChar());
#endif
    }

    // Connect output port RateGroupMemberOut
    for (
      FwIndexType port = 0;
      port < static_cast<FwIndexType>(this->getNum_RateGroupMemberOut_OutputPorts());
      port++
    ) {
      this->m_RateGroupMemberOut_OutputPort[port].init();

#if FW_OBJECT_NAMES == 1
      Fw::ObjectName portName;
      portName.format(
        "%s_RateGroupMemberOut_OutputPort[%" PRI_FwIndexType "]",
        this->m_objName.toChar(),
        port
      );
      this->m_RateGroupMemberOut_OutputPort[port].setObjName(portName.toChar());
#endif
    }
  }

  // ----------------------------------------------------------------------
  // Getters for typed input ports
  // ----------------------------------------------------------------------

  Svc::InputCyclePort* PassiveRateGroupComponentBase ::
    get_CycleIn_InputPort(FwIndexType portNum)
  {
    FW_ASSERT(
      (0 <= portNum) && (portNum < this->getNum_CycleIn_InputPorts()),
      static_cast<FwAssertArgType>(portNum)
    );

    return &this->m_CycleIn_InputPort[portNum];
  }

  // ----------------------------------------------------------------------
  // Connect input ports to special output ports
  // ----------------------------------------------------------------------

  void PassiveRateGroupComponentBase ::
    set_Time_OutputPort(
        FwIndexType portNum,
        Fw::InputTimePort* port
    )
  {
    FW_ASSERT(
      (0 <= portNum) && (portNum < this->getNum_Time_OutputPorts()),
      static_cast<FwAssertArgType>(portNum)
    );

    this->m_Time_OutputPort[portNum].addCallPort(port);
  }

  void PassiveRateGroupComponentBase ::
    set_Tlm_OutputPort(
        FwIndexType portNum,
        Fw::InputTlmPort* port
    )
  {
    FW_ASSERT(
      (0 <= portNum) && (portNum < this->getNum_Tlm_OutputPorts()),
      static_cast<FwAssertArgType>(portNum)
    );

    this->m_Tlm_OutputPort[portNum].addCallPort(port);
  }

  // ----------------------------------------------------------------------
  // Connect typed input ports to typed output ports
  // ----------------------------------------------------------------------

  void PassiveRateGroupComponentBase ::
    set_RateGroupMemberOut_OutputPort(
        FwIndexType portNum,
        Svc::InputSchedPort* port
    )
  {
    FW_ASSERT(
      (0 <= portNum) && (portNum < this->getNum_RateGroupMemberOut_OutputPorts()),
      static_cast<FwAssertArgType>(portNum)
    );

    this->m_RateGroupMemberOut_OutputPort[portNum].addCallPort(port);
  }

#if FW_PORT_SERIALIZATION

  // ----------------------------------------------------------------------
  // Connect serial input ports to special output ports
  // ----------------------------------------------------------------------

  void PassiveRateGroupComponentBase ::
    set_Time_OutputPort(
        FwIndexType portNum,
        Fw::InputSerializePort* port
    )
  {
    FW_ASSERT(
      (0 <= portNum) && (portNum < this->getNum_Time_OutputPorts()),
      static_cast<FwAssertArgType>(portNum)
    );

    this->m_Time_OutputPort[portNum].registerSerialPort(port);
  }

  void PassiveRateGroupComponentBase ::
    set_Tlm_OutputPort(
        FwIndexType portNum,
        Fw::InputSerializePort* port
    )
  {
    FW_ASSERT(
      (0 <= portNum) && (portNum < this->getNum_Tlm_OutputPorts()),
      static_cast<FwAssertArgType>(portNum)
    );

    this->m_Tlm_OutputPort[portNum].registerSerialPort(port);
  }

#endif

#if FW_PORT_SERIALIZATION

  // ----------------------------------------------------------------------
  // Connect serial input ports to typed output ports
  // ----------------------------------------------------------------------

  void PassiveRateGroupComponentBase ::
    set_RateGroupMemberOut_OutputPort(
        FwIndexType portNum,
        Fw::InputSerializePort* port
    )
  {
    FW_ASSERT(
      (0 <= portNum) && (portNum < this->getNum_RateGroupMemberOut_OutputPorts()),
      static_cast<FwAssertArgType>(portNum)
    );

    this->m_RateGroupMemberOut_OutputPort[portNum].registerSerialPort(port);
  }

#endif

  // ----------------------------------------------------------------------
  // Component construction and destruction
  // ----------------------------------------------------------------------

  PassiveRateGroupComponentBase ::
    PassiveRateGroupComponentBase(const char* compName) :
      Fw::PassiveComponentBase(compName)
  {

  }

  PassiveRateGroupComponentBase ::
    ~PassiveRateGroupComponentBase()
  {

  }

  // ----------------------------------------------------------------------
  // Connection status queries for special output ports
  // ----------------------------------------------------------------------

  bool PassiveRateGroupComponentBase ::
    isConnected_Time_OutputPort(FwIndexType portNum)
  {
    FW_ASSERT(
      (0 <= portNum) && (portNum < this->getNum_Time_OutputPorts()),
      static_cast<FwAssertArgType>(portNum)
    );

    return this->m_Time_OutputPort[portNum].isConnected();
  }

  bool PassiveRateGroupComponentBase ::
    isConnected_Tlm_OutputPort(FwIndexType portNum)
  {
    FW_ASSERT(
      (0 <= portNum) && (portNum < this->getNum_Tlm_OutputPorts()),
      static_cast<FwAssertArgType>(portNum)
    );

    return this->m_Tlm_OutputPort[portNum].isConnected();
  }

  // ----------------------------------------------------------------------
  // Connection status queries for typed output ports
  // ----------------------------------------------------------------------

  bool PassiveRateGroupComponentBase ::
    isConnected_RateGroupMemberOut_OutputPort(FwIndexType portNum)
  {
    FW_ASSERT(
      (0 <= portNum) && (portNum < this->getNum_RateGroupMemberOut_OutputPorts()),
      static_cast<FwAssertArgType>(portNum)
    );

    return this->m_RateGroupMemberOut_OutputPort[portNum].isConnected();
  }

  // ----------------------------------------------------------------------
  // Port handler base-class functions for typed input ports
  //
  // Call these functions directly to bypass the corresponding ports
  // ----------------------------------------------------------------------

  void PassiveRateGroupComponentBase ::
    CycleIn_handlerBase(
        FwIndexType portNum,
        Os::RawTime& cycleStart
    )
  {
    // Make sure port number is valid
    FW_ASSERT(
      (0 <= portNum) && (portNum < this->getNum_CycleIn_InputPorts()),
      static_cast<FwAssertArgType>(portNum)
    );

    // Call handler function
    this->CycleIn_handler(
      portNum,
      cycleStart
    );
  }

  // ----------------------------------------------------------------------
  // Invocation functions for typed output ports
  // ----------------------------------------------------------------------

  void PassiveRateGroupComponentBase ::
    RateGroupMemberOut_out(
        FwIndexType portNum,
        U32 context
    )
  {
    FW_ASSERT(
      (0 <= portNum) && (portNum < this->getNum_RateGroupMemberOut_OutputPorts()),
      static_cast<FwAssertArgType>(portNum)
    );

    FW_ASSERT(
      this->m_RateGroupMemberOut_OutputPort[portNum].isConnected(),
      static_cast<FwAssertArgType>(portNum)
    );
    this->m_RateGroupMemberOut_OutputPort[portNum].invoke(
      context
    );
  }

  // ----------------------------------------------------------------------
  // Telemetry write functions
  // ----------------------------------------------------------------------

  void PassiveRateGroupComponentBase ::
    tlmWrite_MaxCycleTime(
        U32 arg,
        Fw::Time _tlmTime
    )
  {
    // Check to see if it is the first time
    if (not this->m_first_update_MaxCycleTime) {
      // Check to see if value has changed. If not, don't write it.
      if (arg == this->m_last_MaxCycleTime) {
        return;
      }
      else {
        this->m_last_MaxCycleTime = arg;
      }
    }
    else {
      this->m_first_update_MaxCycleTime = false;
      this->m_last_MaxCycleTime = arg;
    }

    if (this->m_Tlm_OutputPort[0].isConnected()) {
      if (
        this->m_Time_OutputPort[0].isConnected() &&
        (_tlmTime ==  Fw::ZERO_TIME)
      ) {
        this->m_Time_OutputPort[0].invoke(_tlmTime);
      }

      Fw::TlmBuffer _tlmBuff;
      Fw::SerializeStatus _stat = _tlmBuff.serializeFrom(arg);
      FW_ASSERT(
        _stat == Fw::FW_SERIALIZE_OK,
        static_cast<FwAssertArgType>(_stat)
      );

      FwChanIdType _id;

      _id = this->getIdBase() + CHANNELID_MAXCYCLETIME;

      this->m_Tlm_OutputPort[0].invoke(
        _id,
        _tlmTime,
        _tlmBuff
      );
    }
  }

  void PassiveRateGroupComponentBase ::
    tlmWrite_CycleTime(
        U32 arg,
        Fw::Time _tlmTime
    ) const
  {
    if (this->m_Tlm_OutputPort[0].isConnected()) {
      if (
        this->m_Time_OutputPort[0].isConnected() &&
        (_tlmTime ==  Fw::ZERO_TIME)
      ) {
        this->m_Time_OutputPort[0].invoke(_tlmTime);
      }

      Fw::TlmBuffer _tlmBuff;
      Fw::SerializeStatus _stat = _tlmBuff.serializeFrom(arg);
      FW_ASSERT(
        _stat == Fw::FW_SERIALIZE_OK,
        static_cast<FwAssertArgType>(_stat)
      );

      FwChanIdType _id;

      _id = this->getIdBase() + CHANNELID_CYCLETIME;

      this->m_Tlm_OutputPort[0].invoke(
        _id,
        _tlmTime,
        _tlmBuff
      );
    }
  }

  void PassiveRateGroupComponentBase ::
    tlmWrite_CycleCount(
        U32 arg,
        Fw::Time _tlmTime
    ) const
  {
    if (this->m_Tlm_OutputPort[0].isConnected()) {
      if (
        this->m_Time_OutputPort[0].isConnected() &&
        (_tlmTime ==  Fw::ZERO_TIME)
      ) {
        this->m_Time_OutputPort[0].invoke(_tlmTime);
      }

      Fw::TlmBuffer _tlmBuff;
      Fw::SerializeStatus _stat = _tlmBuff.serializeFrom(arg);
      FW_ASSERT(
        _stat == Fw::FW_SERIALIZE_OK,
        static_cast<FwAssertArgType>(_stat)
      );

      FwChanIdType _id;

      _id = this->getIdBase() + CHANNELID_CYCLECOUNT;

      this->m_Tlm_OutputPort[0].invoke(
        _id,
        _tlmTime,
        _tlmBuff
      );
    }
  }

  // ----------------------------------------------------------------------
  // Time
  // ----------------------------------------------------------------------

  Fw::Time PassiveRateGroupComponentBase ::
    getTime() const
  {
    if (this->m_Time_OutputPort[0].isConnected()) {
      Fw::Time _time;
      this->m_Time_OutputPort[0].invoke(_time);
      return _time;
    }
    else {
      return Fw::Time(TimeBase::TB_NONE, 0, 0);
    }
  }

  // ----------------------------------------------------------------------
  // Calls for messages received on typed input ports
  // ----------------------------------------------------------------------

  void PassiveRateGroupComponentBase ::
    m_p_CycleIn_in(
        Fw::PassiveComponentBase* callComp,
        FwIndexType portNum,
        Os::RawTime& cycleStart
    )
  {
    FW_ASSERT(callComp);
    PassiveRateGroupComponentBase* compPtr = static_cast<PassiveRateGroupComponentBase*>(callComp);
    compPtr->CycleIn_handlerBase(
      portNum,
      cycleStart
    );
  }

}